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functional block diagram 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad674b/ad774b 5v supply v logic data mode select 12/ 8 chip select cs byte address/ short cycle a 0 read/convert r/ c chip enable ce 12v/15v supply v cc 10v reference ref out analog common ac reference input ref in ?2v/?5v supply v ee bipolar offset bipoff 10v span input 10v in 20v span input 20v in status sts db11 (msb) db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) digital common dc control vo ltag e divider n y b b l e a msb 3 s t a t e o u t p u t b u f f e r s lsb n y b b l e b n y b b l e c clock sar 12 10v ref + comp i dac + 199.95 k dac n v ee i ref digital data outputs rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a complete 12-bit a/d converters ad674b /ad774b features complete monolithic 12-bit a/d converters with reference, clock, and three-state output buffers industry standard pinout high speed upgrades for ad574a 8- and 16-bit microprocessor interface 8 s (max) conversion time (ad774b) 15 s (max) conversion time (ad674b) 5 v, 10 v, 0 vC10 v, 0 vC20 v input ranges commercial, industrial, and military temperature range grades mil-std-883-compliant versions available product description the ad674b and ad774b are complete 12-bit successive- approximation analog-to-digital converters with three-state output buffer circuitry for direct interface to 8- and 16-bit microprocessor busses. a high-precision voltage reference and clock are included on chip, and the circuit requires only power supplies and control signals for operation. the ad674b and ad774b are pin-compatible with the indus- try standard ad574a, but offer faster conversion time and bus- access speed than the ad574a and lower power consumption. the ad674b converts in 15 s (maximum) and the ad774b converts in 8 s (maximum). the monolithic design is implemented using analog devices bimos ii process allowing high-performance bipolar analog circuitry to be combined on the same die with digital cmos logic. offset, linearity, and scaling errors are minimized by active laser trimming of thin-film resistors. five different grades are available. the j and k grades are specified for operation over the 0 c to 70 c temperature range. the a and b grades are specified from C40 c to +85 c, the t grade is specified from C55 c to +125 c. the j and k grades are available in a 28-lead plastic dip or 28-lead soic. all other grades are available in a 28-lead hermetically sealed ceramic dip. product highlights 1. industry standard pinout: the ad674b and ad774b use the pinout established by the industry standard ad574a. 2. analog operation: the precision, laser-trimmed scaling and bipolar offset resistors provide four calibrated ranges: 0 v to 10 v and 0 v to 20 v unipolar; C5 v to +5 v and C10 v to +10 v bipolar. the ad674b and ad774b operate on +5 v and 12 v or 15 v power supplies. 3. flexible digital interface: on-chip multiple-mode three-state output buffers and interface logic allow direct connection to most microprocessors. the 12 bits of output data can be read either as one 12-bit word or as two 8-bit bytes (one with 8 data bits, the other with 4 data bits and 4 trailing zeros). 4. the internal reference is trimmed to 10.00 v with 1% maxi- mum error and 10 ppm/ c typical temperature coefficient. the reference is available externally and can drive up to 2.0 ma beyond the requirements of the converter and bipo- lar offset resistors. 5. the ad674b and ad774b are available in versions compli- ant with mil-std-883. refer to the analog devices mili- tary products databook or current ad674b/ad774b/883b data sheet for detailed specifications. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002
j grade k grade a grade b grade t grade model (ad674b or ad774b) min typ max min typ max min typ max min typ max min typ max unit resolution 12 12 12 12 12 bits linearity error @ 25 c 1 1/2 1 1/2 1/2 lsb t min to t max 1 1/2 1 1/2 1 lsb differential linearity error (minimum resolution for which no missing codes are guaranteed) 12 12 12 12 12 bits unipolar offset 1 @ 25 c 2 2 2 2 2 lsb bipolar offset 1 @ 25 c 6 3 6 3 3 lsb full-scale calibration error 1, 2 @ 25 c (with fixed 50 resistor from ref out to ref in) 0.1 0.25 0.1 0.125 0.1 0.25 0.1 0.125 0.1 0.125 % of fs temperature range 0 70 0 70 e40 +85 e40 +85 e55 +125 c temperature drift 3 (using internal reference) unipolar 2 1 2 1 1 lsb bipolar offset 2 1 2 1 2 lsb full-scale calibration 6 2 8 5 7 lsb power supply rejection max change in full-scale calibration v cc = +15 v 1.5 v or +12 v 0.6 v 2 1 2 1 1 lsb v logic = +5 v 0.5 v 1/2 1/2 1/2 1/2 1/2 lsb v ee = e15 v 1.5 v or e12 v 0.6 v 2 1 2 1 1 lsb analog input input ranges bipolar e5 +5 e5 +5 e5 +5 e5 +5 e5 +5 v e10 +10 e10 +10 e10 +10 e10 +10 e10 +10 v unipolar 0 10 0 10 0 10 0 10 0 10 v 0 20 0 20 0 20 0 20 0 20 v input impedance 10 v span 3 5 73 5 73 5 73 5 73 5 7 k 20 v span 6 10 14 6 10 14 6 10 14 6 10 14 6 10 14 k power supplies operating range v logic 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 v v cc 11.4 16.5 11.4 16.5 11.4 16.5 11.4 16.5 11.4 16.5 v v ee e16.5 e11.4 e16.5 e11.4 e16.5 e11.4 e16.5 e11.4 e16.5 e11.4 v operating current i logic 3.5 7 3.5 7 3.5 7 3.5 7 3.5 7 ma i cc 3.5 7 3.5 7 3.5 7 3.5 7 3.5 7 ma i ee 10 14 10 14 10 14 10 14 10 14 ma power consumption 220 375 220 375 220 375 220 375 220 375 mw 4 175 175 175 175 175 mw 5 internal reference voltage 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 v output current (available for external loads) 2.0 2.0 2.0 2.0 2.0 ma (external load should not change during the conversion) notes 1 adjustable to zero. 2 includes internal voltage reference error. 3 maximum change from 25 c value to the value at t min or t max . 4 tested with ref out tied to ref in through 50 resistor, v cc = +16.5 v, v ee = e16.5 v, v logic = +5.5 v, and outputs in high-z mode. 5 tested with ref out tied to ref in through 50 resistor, v cc = +12 v, v ee = e12 v, v logic = +5 v, and outputs in high-z mode. specifications subject to change without notice. specifications shown in boldface are tested on all devices at final electrical test at t min , 25 c, and t max . results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested. ad674b/ad774bespecifications (t min to t max with v cc = +15 v 10% or +12 v 5%, v logic = +5 v 10%, v ee = e15 v 10% or e12 v 5%, unless otherwise noted.) #$#
#%# converter start timing (figure 1) j, k, a, b grades t grade parameter symbol min typ max min typ max unit conversion time 8-bit cycle (ad674b) t c 68 10 68 10 s 12-bit cycle (ad674b) t c 912 15 912 15 s 8-bit cycle (ad774b) t c 45 6 45 6 s 12-bit cycle (ad774b) t c 6 7.3 8 6 7.3 8 s sts delay from ce t dsc 200 225 ns ce pulsewidth t hec 50 50 ns cs cs c c cs c cs c s s s s c c c t hec t hsc t ssc t hrc t src t sac t hac t c t dsc ce r/ a 0 sts db11 e db0 high impedance &
'
(
) t ssr ce r/ a 0 sts db11 e db0 t hsr t hrr t har t hd t sar t srr high impedance data va l i d high impedance t hl t dd &
$) db n 3k 100pf db n 3k 100pf 5v high-z to logic 0 high-z to logic 1 *+ , '*+ , - &
%,

)) db n 3k 100pf logic 1 to high-z db n 3k 100pf 5v logic 0 to high-z , ' *+, - *+ &
%,

. & ) ad674b/ad774b
rev. c C4C ad674b/ad774b timing?tand alone mode (figures 4a and 4b) j, k, a, b grades t grade parameter symbol min typ max min typ max unit data access time t ddr 150 150 ns low r/ c pulsewidth t hrl 50 50 ns sts delay from r/ c t ds 200 225 ns data valid after r/ c low t hdr 25 25 ns sts delay after data valid t hs 30 200 600 30 200 600 ns high r/ c pulsewidth t hrh 150 150 ns specifications subject to change without notice. absolute maximum ratings * v cc to digital common . . . . . . . . . . . . . . . . . . . 0 to +16.5 v v ee to digital common . . . . . . . . . . . . . . . . . . . . 0 to C 16.5 v v logic to digital common . . . . . . . . . . . . . . . . . . . 0 to +7 v analog common to digital common . . . . . . . . . . . . . . . 1 v digital inputs to digital common . . . C 0.5 v to v logic +0.5 v analog inputs to analog common . . . . . . . . . . . . v ee to v cc 20 v in to analog common . . . . . . . . . . . . . . . . . . . . . . 24 v ref out . . . . . . . . . . . . . . . . . . indefinite short to common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . momentary short to v cc junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mw lead temperature, soldering (10 sec) . . . . . . . . . . . . . 300 c storage temperature . . . . . . . . . . . . . . . . . . C 65 c to +150 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. r/ c sts db11 e db0 data va l i d data valid t hrl t ds high e z t hs t hdr t c flgure 4a. standalone mode timing low pulse r/ c r/ c sts db11 e db0 high e z high e z data va l i d t hrh t ds t ddr t hdr t c t hl figure 4b. standalone mode timing high pulse for r/ c warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad674b/ad774b features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide conversion inl package package model l temperature time (max) (t min to t max ) description option 2 ad674bjn 0 c to 70 c 15 s 1 lsb plastic dip n-28 ad674bkn 0 c to 70 c 15 s 1/2 lsb plastic dip n-28 ad674bar C 40 c to +85 c 15 s 1 lsb plastic soic r-28 ad674bbr C 40 c to +85 c 15 s 1/2 lsb plastic soic r-28 ad674bad C 40 c to +85 c 15 s 1 lsb ceramic dip d-28 ad674bbd C 40 c to +85 c 15 s 1/2 lsb ceramic dip d-28 ad674btd C 55 c to +125 c 15 s 1 lsb ceramic dip d-28 ad774bjn 0 c to 70 c8 s 1 lsb plastic dip n-28 ad774bkn 0 c to 70 c8 s 1/2 lsb plastic dip n-28 ad774bar C 40 c to +85 c8 s 1 lsb plastic soic r-28 ad774bbr C 40 c to +85 c8 s 1/2 lsb plastic soic r-28 ad774bad C 40 c to +85 c8 s 1 lsb ceramic dip d-28 ad774bbd C 40 c to +85 c8 s 1/2 lsb ceramic dip d-28 ad774btd C 55 c to +125 c8 s 1 lsb ceramic dip d-28 notes 1 for details on grade and package offerings screened in accordance with mil-std-883, refer to the analog devices military products databook or the current ad674b/ ad774b/883b data sheet. 2 n = plastic dip; d = hermetic dip; r = plastic soic.
#3# definition of specifications linearity error linearity error refers to the deviation of each individual code from a line drawn from zero through full scale. the point used as zero occurs 1/2 lsb (1.22 mv for 10 v span) before the first code transition (all zeroes to only the lsb on ). full scale is defined as a level 1 1/2 lsb beyond the last code tran- sition (to all ones). the deviation of a code from the true straight line is measured from the middle of each particular code. the k, b, and t grades are guaranteed for maximum nonlinear- ity of 1/2 lsb. for these grades, this means that an analog value that falls exactly in the center of a given code width will result in the correct digital output code. values nearer the upper or lower transition of the code width may produce the next upper or lower digital output code. the j and a grades are guaranteed to 1 lsb max error. for these grades, an analog value that falls within a given code width will result in either the correct code for that region or either adjacent one. note that the linearity error is not user adjustable. differential linearity error (no missing codes) a specification that guarantees no missing codes requires that every code combination appear in a monotonic increasing sequence as the analog input level is increased. thus every code must have a finite width. the ad674b and ad774b guarantee no missing codes to 12-bit resolution, requiring that all 4096 codes must be present over the entire operating temperature ranges. unipolar offset the first transition should occur at a level 1/2 lsb above analog common. unipolar offset is defined as the deviation of the actual transition from that point. this offset can be adjusted as dis cussed later. the unipolar offset temperature coefficient specifies the maximum change of the transition point over tem perature, with or without external adjustment. bipolar offset in the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 lsb below analog common. the bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. quantization uncertainty analog-to-digital converters exhibit an inherent quantization uncertainty of 1/2 lsb. this uncertainty is a fundamental characteristic of the quantization process and cannot be reduced for a converter of given resolution. left-justified data the output data format is left-justified. this means that the data represents the analog input as a fraction of full scale, rang- ing from 0 to 4095/4096. this implies a binary point 4095 to the left of the msb. full-scale calibration error the last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1/2 lsb below the nominal full scale (9.9963 v for 10.000 v full scale). the full-scale cali- bration error is the deviation of the actual level at the last transi- tion from the ideal level. this error, which is typically 0.05% to 0.1% of full scale, can be trimmed out as shown in figures 7 and 8. the full-scale calibration error over temperature is given with and without the initial error trimmed out. the temperature coefficients for each grade indicate the maximum change in the full-scale gain from the initial value using the internal 10 v reference. temperature drift the temperature drift for full-scale calibration, unipolar offset, and bipolar offset specifies the maximum change from the initial (25 c) value to the value at t min or t max . power supply rejection the standard specifications assume use of +5.00 v and 15.00 v or 12.00 v supplies. the only effect of power supply error on the performance of the device will be a small change in the full-scale calibration. this will result in a linear change in all low-order codes. the specifications show the maximum full- scale change from the initial value with the supplies at the vari ous limits. code width a fundamental quantity for a/d converter specifications is the code width. this is defined as the range of analog input values for which a given digital output code will occur. the nominal value of a code width is equivalent to 1 least significant bit (lsb) of the full-scale range or 2.44 mv out of 10 v for a 12-bit adc. ad674b/ad774b
#4# ad674b/ad774b pin function descriptions symbol pin no. type name and function agnd 9 p analog ground (common) a 0 4 di byte address/short cycle. if a conversion is started with a 0 active low, a full 12-bit conversion cycle is initiated. if a 0 is active high during a convert start, a shorter 8-bit conversion cycle results. during read (r/ c 8 cs 8 c c c 8 8 8 8 top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad674b or ad774b v logic 12/ a 0 r/ ce v cc ref out agnd ref in v ee bip off 10 v in 20 v in sts db11 (msb) db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) dgnd
#5# circuit operation the ad674b and ad774b are complete 12-bit monolithic a/d converters that require no external components to provide the complete successive-approximation analog-to-digital conversion function. a block diagram is shown in figure 5. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad674b/ad774b 5v supply v logic data mode select 12/ chip select byte address/ short cycle a 0 read/convert r/ chip enable ce 12v/15v supply v cc 10v reference ref out analog common ac reference input ref in e 12v/ e 15v supply v ee bipolar offset bipoff 10v span input 10v in 20v span input 20v in status sts db11 (msb) db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) digital common dc control vo ltag e divider n y b b l e a msb 3 s t a t e o u t p u t b u f f e r s lsb n y b b l e b n y b b l e c clock sar 12 10v ref e + comp i dac e + 199.95 k dac n v ee i ref digital data outputs &
3 6 7
45/655/6 when the control section is commanded to initiate a conversion (as described later) it enables the clock and resets the succes sive-approximation register (sar) to all zeroes. once a conversion cycle has begun, it cannot be stopped or restarted and data is not available from the output buffers. the sar, timed by the clock, will sequence through the conversion cycle and return an end-of-convert flag to the control section. the control section will then disable the clock, bring the output status flag low, and enable control functions to allow data read by external command. during the conversion cycle, the internal 12-bit current output dac is sequenced by the sar from the most significant bit (msb) to least significant bit (lsb) to provide an output cur- rent that accurately balances the input signal current through the divider network. the comparator determines whether the addition of each successively weighted bit current causes the dac current sum to be greater or less than the input current; if the sum is less, the bit is left on; if more, the bit is turned off. after testing all the bits, the sar contains a 12-bit binary code that accurately represents the input signal to within 1/2 lsb. the temperature-compensated reference provides the primary voltage reference to the dac and guarantees excellent stability with both time and temperature. the reference is trimmed to 10.00 v 1%; it can supply up to 2.0 ma to an external load in addition to the requirements of the reference input resistor (0.5 ma) and bipolar offset resistor (0.5 ma). any external load on the reference must remain constant during conversion. the thin-film application resistors are trimmed to match the full- scale output current of the dac. the input divider network provides a 10 v or 20 v input range. the bipolar offset resistor is grounded for unipolar operation and connected to the 10 v reference for bipolar operation. driving the analog input the ad674b and ad774b are successive-approximation ana log- to-digital converters. during the conversion cycle, the adc input current is modulated by the dac test current at approximately a 1 mhz rate. thus it is important to recognize that the signal source driving the adc must be capable of holding a constant output voltage under dynamically changing load conditions. current output dac analog common current limiting resistors feedback to amplifier adc comparator i in i test r in i diff i in is modulated by changes in test current. amplifier pulse load response limited by open-loop output impedance. v e v+ sar &
4 . 8
the closed-loop output impedance of an op amp is equal to the open-loop output impedance (usually a few hundred ohms) divided by the loop gain at the frequency of interest. it is often assumed that the loop gain of a follower-connected op amp is sufficiently high to reduce the closed-loop output impedance to a negligibly small value, particularly if the signal is low fre- quency. however, the amplifier driving the adc must either have sufficient loop gain at 1 mhz to reduce the closed-loop output impedance to a low value or have low open-loop output impedance. this can be accomplished by using a wideband op amp, such as the ad711. if a sample-hold amplifier is required, the monolithic ad585 or ad781 is recommended, with the output buffer driving the ad674b or ad774b input directly. a better alternative is the ad1674, which is a 10 s sampling adc in the same pinout as the ad574a, ad674a, or ad774b and is functionally equivalent. supply decoupling and layout consideration it is critical that the power supplies be filtered, well regulated, and free from high-frequency noise. use of noisy supplies will cause unstable output codes. switching power supplies is not recommended for circuits attempting to achieve 12-bit accuracy unless great care is used in filtering any switching spikes present in the output. few millivolts of noise represent several counts of error in a 12-bit adc. decoupling capacitors should be used on all power supply pins; the 5 v supply decoupling capacitor should be connected di rectly from pin 1 to pin 15 (digital common) and the +v cc and e v ee pins should be decoupled directly to analog common (pin 9). a suitable decoupling capacitor is a 4.7 f tantalum type in paral- lel with a 0.1 f ceramic disc type. ad674b/ad774b
#9# ad674b/ad774b circuit layout should attempt to locate the adc, associated analog input circuitry, and interconnections as far as possible from logic circuitry. for this reason, the use of wire-wrap circuit construction is not recommended. careful printed-circuit layout and manufacturing is preferred. unipolar range connections for the ad674b and ad774b the ad674b and ad774b contain all the active components required to perform a complete 12-bit a/d conversion. thus, for most situations, all that is necessary is connection of the power supplies (+5 v, +12/+15 v, and e 12/ e 15 v), the analog input, and the conversion initiation command, as discussed on the next page. 2 3 4 5 6 8 12 13 10 14 9 ad674b/ad774b sts 28 high bits 24 e 27 middle bits 20 e 23 low bits 16 e 19 +15v 7 e 15v 11 dig com 15 +5v 1 100 r2 gain r1 100k offset +12v/ +15v e 12v/ e 15v 100k 100 0 to 10v analog inputs 0 to 20v 12/ a 0 r/ ce ref out bip off 10v in ref in 20v in ana com &
5 :
all of the thin-film application resistors of the ad674b and ad774b are factory trimmed for absolute calibration. there fore, in many applications, no calibration trimming will be required. the absolute accuracy for each grade is given in the specifica tion tables. for example, if no trims are used, 2 lsb max zero offset error and 0.25% (10 lsb) max full-scale error are guaranteed. if the offset trim is not required, pin 12 can be connected di rectly to pin 9; the two resistors and trimmer for pin 12 are then not needed. if the full-scale trim is not required, a 50 1% metal film resistor should be connected between pin 8 and pin 10. the analog input is connected between pins 13 and 9 for a 0 v to 10 v input range, between pins 14 and 9 for a 0 v to 20 v input range. input signals beyond the supplies are easily accommo- dated. for the 10 v span input, the lsb has a nominal value of 2.44 mv; for the 20 v span, 4.88 mv. if a 10.24 v range is desired (nominal 2.5 mv/bit), the gain trimmer (r2) should be replaced by a 50 resistor and a 200 trimmer inserted in series with the analog input to pin 13 (for a full-scale range of 20.48 v [5 mv/bit] use a 500 trimmer into pin 14). the gain trim de scribed below is now done with these trimmers. the nominal input impedance into pin 13 is 5 k , and into pin 14 is 10 k . unipolar calibration the connections for unipolar ranges are shown in figure 7. the ad674b or ad774b is trimmed to a nominal 1/2 lsb offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes above and below it). thus, when properly calibrated, the first transi tion (from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 lsb (1.22 mv for 10 v range). if pin 12 is connected to pin 9, the unit will behave in this man ner, within specifications. if the offset trim (r1) is used, it should be trimmed as above, although a different offset can be set for a particular system requirement. this circuit will give approxim ately 15 mv of offset trim range. the full-scale trim is done by applying a signal 1 1/2 lsb below the nominal full scale (9.9963 for a 10 v range). trim r2 to give the last transition (1111 1111 1110 to 1111 1111 1111). bipolar operation the connections for bipolar ranges are shown in figure 8. again, as for the unipolar ranges, if the offset and gain specifica- tions are sufficient, one or both of the trimmers shown can be replaced by a 50 1% fixed resistor. the analog input is applied as for the unipolar ranges. bipolar calibration is similar to unipolar calibration. first, a signal 1/2 lsb above negative full scale ( e 4.9988 v for the 5 v range) is applied and r1 is trimmed to give the first transition (0000 0000 0000 to 0000 0000 0001). then a signal 1 1/2 lsb below positive full scale (+4.9963 v for the 5 v range) is applied and r2 trimmed to give the last transition (1111 1111 1110 to 1111 1111 1111). ad674b/ad774b high bits 24 e 27 middle bits 20 e 23 low bits 16 e 19 100 r2 gain analog inputs 10v r1 100 offset 5v 2 3 4 5 6 8 12 13 10 14 9 sts 28 +15v 7 e 15v 11 dig com 15 +5v 1 12/ a 0 r/ ce ref out bip off 10v in ref in 20v in ana com &
9 6
grounding considerations the analog common at pin 9 is the ground reference point for the internal reference and is thus the high quality ground for the adc; it should be connected directly to the analog refer ence point of the system. to achieve the high-accuracy performance available from the adc in an environment of high digital noise content, the analog and digital commons must be connected together at the package. in some situations, the digital common at pin 15 can be connected to the most convenient ground ref- erence point; digital power return is preferred.
#;# to output buffers ce r/ a 0 12/ nybble a enable nybble b enable nybble c enable nybble = 0 enable status clk en high if conversion in progress sar reset eoc 12 eoc 8 start convert s r q qb value of a 0 at last convert command d en d en q r s q &
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,

control logic the ad674b and ad774b contain on-chip logic to provide conversion initiation and data read operations from signals commonly available in microprocessor systems; this internal logic circuitry is shown in figure 9. the control signals ce, cs c c cs c c 8 8 8 8 cs c 8 cs c cs c cs c c c cs c
#'-# ad674b/ad774b standalone mode standalone mode is useful in systems with dedicated input ports available and thus not requiring full bus interface capabil- ity. standalone mode applications are generally able to issue conversion start commands more precisely than full-control mode, resulting in improved accuracy. ce and 12/ 8 cs c c c c c c c c 8 8 8 8 8 8 8 db11 (msb) db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) 0000 d7 d0 xxx0 (even addr) xxx1 (odd addr) &
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9*6 6
#''# outline dimensions dimensions shown in inches and (mm). 28-lead ceramic dip package (d-28) 1.42 (36.07) 1.40 (35.56) 28 1 15 14 0.59 0.01 (14.98) + e 0.050 (12.83) 0.085 (2.16) 0.017 0.003 (0.43) + e 0.1 (2.54) 0.047 0.007 (1.19) + e 0.095 (2.41) 0.050 0.010 (1.27) + e 0.6 (15.24) 0.010 0.002 (0.254 0.05) + e + e 0.145 0.02 (3.68) + e 0.08 (2.0) 0.125 min (3.17) seating plane 30 o 0.05 (1.27) 0.045 (1.14) 28-lead plastic dip package (n-28) 0.195 (4.95) 0.125 (3.18) 0.015 (0.381) 0.008 (0.204) 0.625 (15.87) 0.600 (15.24) 28 114 15 pin 1 0.580 (14.73) 0.485 (12.32) 1.565 (39.70) 1.380 (35.10) seating plane 0.060 (1.52) 0.015 (0.38) 0.250 (6.35) max 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) min 0.100 (2.54) bsc 0.070 (1.77) max 28-lead wide body soic package (r-28) 0.0125 (0.32) 0.0091 (0.23) 8 0 0.0291 (0.74) 0.0098 (0.25) 45 0.0500 (1.27) 0.0157 (0.40) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 28 15 14 1 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 ad674b/ad774b
#'$# ad674b/ad774b --9-9*-*/2-$=> 1!)!:( revision history location page data sheet changed from rev. b to rev. c. edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 add 28-lead wide body soic package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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